The use of DRAM technology has become widespread, especially in higher end system designs, because of its superior performance, silicon-area savings, and low power compared with discrete-memory approaches. A highly integrated DRAM approach also simplifies board design, thereby reducing overall system cost and time to market. Even more important, embedding DRAM enables higher bandwidth by allowing larger on-chip memory and a wider on-chip bus and saves power by eliminating DRAM I/O buffers. Today, designers can take advantage of these capabilities as various high density DRAM technologies enter production. However, DRAM cells utilizing these technologies are susceptible to a large amount of process variation due to factors such as threshold voltage variation and mismatch. It is this process variation that creates limitations on the design and fabrication of the DRAM and the associated systems.
Thus, there is a need to provide monitoring for measuring statistics of important DRAM parameters in order to control the inherent process variation.